Friedrichshafen, Nuremberg -- At Embedded World 2026, ZF and SiliconAuto debuted a new I/O interface chip and microcontroller design for automotive high-performance computers. The companies said it's the world’s first live demonstration of real-time sensor data acquisition and pre-processing on silicon to enable the next generation of autonomous driving.
The demonstration is based on a new ZF I/O interface chip design with SiliconAuto's XMotiv M3 microcontroller used as a safety controller. The new chip architecture represents a new alternative to current monolithic System-on-Chip (SoC) from established providers, offering a scalable and high-performance pathway for the next generation of autonomous driving systems.
ZF collaborated with SiliconAuto to demonstrate an automotive high-performance compute solution for Advanced Driver Assist Systems (ADAS) and Automated Driving (AD). The solution is based on a new I/O interface chip that integrates all required automotive sensor‑interface intellectual property (IP), along with sensor pre‑processing capabilities such as low‑latency camera Image Signal Processing (ISP) and on‑chip radar signal processing.
The Interface Chip is tightly coupled with SiliconAuto’s XMotiv M3 microcontroller and is agnostic to the OEM’s preferred performance SoC, enabled by standardized high‑speed parallel interfaces like PCIe or Ethernet.
The solution offers clear scalability for automotive high-performance computers from the entry segment up to premium vehicles. It also reduces power consumption by limiting data transfers to Double Data Rate (DDR) memory and by reducing clock speeds. The I/O interface chip provides the flexibility to connect to any generation of the latest low‑power AI inference engines.
The chip is manufactured in a lower-cost processing node and offloads sensor data acquisition tasks and sensor data pre-processing to free-up expensive central processing unit (CPU) power on the performance SoC. As such, the expensive application cores of the performance of SoC can fully concentrate on perception and driving functions.
The solution is designed with the potential for future upgradeability to new vehicle generations, enabling one or several chips/chiplets to be updated, possibly without the need for a complete redesign.
The new chip can reduce CPU load, improving overall system efficiency, and providing a scalable path from entry‑level ADAS systems up to SAE Level 4 automated driving.
For more information, visit https://www.zf.com/.
